𝐑𝐞𝐬𝐩𝐨𝐧𝐬𝐢𝐛𝐢𝐥𝐢𝐭𝐢𝐞𝐬:
➛Derive circuit block level specifications.
➛Conduct optimized transistor-level design.
➛Perform Spice simulations.
➛Guide layout design for optimal performance.
➛Characterize designs in PVT + mismatch corners.
➛Generate/deliver behavioral, timing, and physical models.
➛Conduct design reviews at different phases.